Numerical Simulation and Analytical Modeling of Strong-Inversion Gate Capacitance in Ultra-Short (30nm) MOSFETs

Bulk and novel MOSFET structures with gate-lengths in the 30nm regime are expected to become industry standards in ~2007. As devices are scaled down to these lengths, overlapand fringe-capacitance between the gate and source/drain regions gain more importance as a fraction of the total gate-capacitance. Therefore in numerical simulations of these structures it is necessary to carefully include various parasitic capacitance components. Further, finite doping levels in poly-gates lead to appreciable polydepletion effects. For the 30nm MOSFET, the inclusion of the actual gate thickness and dielectric overlayer in the simulation increases fringing capacitance by ~6X, compared to an infinitesimally thin gate and no overlayer. Analytical expressions for these strong inversion capacitance components are useful in device design and circuit simulation. We have derived analytical capacitance formulae for various geometric configurations, which yield values that match numerical simulations quite well.